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Tengfei Jiang Tengfei Jiang, Ph.D.
Assistant Professor, MSE
E-mail: Tengfei.Jiang@ucf.edu
Phone: 407-823-2284
Homepage: http://mse.ucf.edu/jiang

Education

  • Ph.D. — Materials Science and Engineering, The University of Texas at Austin
  • M.S. — Materials Science and Engineering, The Ohio State University
  • B.E. — Materials Science and Engineering, Tsinghua University

Research

  • Reliability metrology
  • Emerging interconnect and packaging systems
  • Micro/nano-fabrication
  • Microstructure and interface
  • Micro/nano-mechanical characterization
  • Synchrotron x-ray microdiffraction

Dr. Jiang’s research interests encompass fundamental materials science, metrology, advanced interconnect and packaging systems, and nanotechnology. The approach is to combine experiments and modeling to investigate and optimize materials, processing, and reliability for micro- and nano-scale devices. Current areas of interest include 3D interconnect and packaging, silicon nanostructures and devices, and advanced manufacturing at micro/nano-scales.

New materials, design, and process integration bring about new and complex reliability challenges for micro/nano scale devices. The fundamental failure physics and mechanisms can be traced to thermal stresses, fracture, wear, and corrosion at nanoscale, and will be investigated using advanced techniques. These include high resolution synchrotron x-ray microdiffraction, nanoindentation, micro-Raman spectroscopy, electron backscatter diffraction, and transmission electron microscopy. The effects of microstructure and interface which play an important role in controlling device reliability will be investigated. These studies will be combined with thermo-mechanical modeling and accelerated tests under temperature/current stressing. The objective is to provide basic understanding to guide materials and processing optimization for better device reliability and faster product development.

Emerging nanomaterials and nanostructures possess unique properties for applications in electronics, biomedical, and energy research. This part of research involves fabrication of nano-scale structures and devices and characterization of mechanical properties of materials and interfaces at small scales. Microstructure and interfaces will be optimized to improve the performance and reliability of devices. Current studies include synthesis of silicon nanostructures with atomic smooth surfaces and high aspect ratio and development of novel thermal interface materials. Potential applications are being developed for microfluidics and sensors.

Selected Publications

T. Jiang, J. Im, R. Huang, and P.S. Ho, “TSV Stress Characteristics and Reliability Impact for 3D Integrated Circuits”, MRS Bulletin, 40 (3), pp 248 - 256 (2015) (invited review paper).

T. Jiang, C. Wu, J. Im, R. Huang, P. S. Ho, “Impact of Grain Structure and Material Properties on Via Extrusion in 3-D Interconnects”, Journal of Microelectronics and Electronic Packaging, in print, 2015.

T. Jiang, C. Wu, N. Tamura, M. Kunz, B. G. Kim, H-Y. Son, M.-S. Suh, J. Im, R. Huang, and P. S. Ho, “Study of Stresses and Plasticity in Through-Silicon Via Structures for 3D Interconnects by X-Ray Micro-Beam Diffraction”, IEEE Trans. on Device and Materials Reliability, 14(2), pp. 698-703 (2014).

S.K. Ryu, T. Jiang, J. Im, R. Huang, and P.S. Ho, “Thermomechanical Failure Analysis of Through-Silicon Via Interface Using a Shear-Lag Model With Cohesive Zone”, IEEE Trans. on Device and Materials Reliability, 14(1), pp.318-326 (2014).

S.K. Ryu, T. Jiang, J. Im, R. Huang and P.S. Ho, “Thermal Stress in 3-D Packaging”, Encyclopedia of Thermal Stresses, R.B. Hetnarski Ed., pp 5208-5217 (2014). Springer Dordrecht, Heidelberg, New York, London.

T. Jiang, C. Wu, L. Spinella, J. Im, N. Tamura, M. Kunz, H-Y. Son, B. G. Kim, R. Huang, and P.S. Ho, “Plasticity Mechanism for Copper Extrusion in Through-Silicon Vias for Three-Dimensional Interconnects”, Appl. Phys. Lett., 103, 211906 (2013).

T. Jiang, S.K. Ryu, Q. Zhao, J. Im, R. Huang, and P.S. Ho, “Measurement and Analysis of Thermal Stresses in 3D Integrated Structures Containing Through-Silicon-Vias”, Microelectron Reliab., 53, pp. 53-62 (2013).

S.K. Ryu, T. Jiang, K.H. Lu, J. Im, H.-Y. Son, K.-Y. Byun, R. Huang, and P.S. Ho, “Characterization of Thermal Stresses in Through-Silicon Vias for Three-Dimensional Interconnects by Bending Beam Technique”, Appl. Phys. Lett., 100, 041901 (2012).

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